The disclosed invention relates generally to the field of circuit board testing and more specifically to the art of testing telecommunications circuit boards. Generally, a given circuit board consists of numerous semiconductor chips, such as a microprocessor, memory chips, counter chips, control chips, etc., laid out according to some interactive design. Following design and layout of the circuit board, it is necessary to test the board to ensure that all the chips, as laid out, perform as expected. Testing will involve application of test-vectors to pins of a given chip (or cluster of chips) on the board. A test-vector for a given chip (or cluster of chips) generally consists of a binary word having an "input" portion and an "output" portion. The goal in testing is to determine if the application of the input portion of a test-vector produces an output matching the output portion of the test-vector. If there is a match, the test is successful (pass). Unsuccessful tests (failure) indicate defective board design, defective layout or defective chips. Test-vectors will be supplied by the designer of the circuit board (usually with the aid of a computer-aided-design (CAD) system). The test-vectors will be chosen so as to pinpoint problems on the board, if they exist.
Actual circuit board testing is performed with the aid of a circuit board testing machine. Circuit board testing machines are well known in the prior art. For example, a well known circuit board testing machine is the Hewlett-Packard Company model HP-3065 circuit board tester. The HP-3065, for instance, has 264 pins which can be simultaneously selectively connected to various pins of a given circuit board for application of test-vectors to the board and the monitoring of board output generated in response. The HP-3065 is fully described in the October 1984 issue of the Hewlett-Packard Journal. With the aid of a circuit board tester, whole sequences of test-vectors are applied to the board under test. In fact, it is not uncommon for test-vector listings to be thousands of test-vectors long where each test-vector is dozens of bits in width. Typically, such test-vectors are applied, sequentially one test vector at a time, in parallel to the circuit board under test.
Telecommunication circuit boards, however, present a special problem in circuit board testing: serial data protocols. Essentially all modern telecommunication schemes obey some sort of serial data protocol, such as the X.25 (HDLC) protocol for wide area networks, the Integrated Services Digital Network ISDN S-Bus protocol (CCITT I.430), the 24-channel U.S. T1 telephone protocol, and so forth. Common to all such protocols is the organization of information in the form of serial frames. The protocol defines the structure of the frame. Consider, for instance, the 24-channel U.S. T1 telephone protocol: analog voice signals are sampled and the samples are digitized; each digitized sample consists of one byte of information; samples are grouped in a 24-channel serial frame; each frame is 193 bits long consisting of a lead framing bit followed by 24 bytes, where each byte is a single sample from a given channel. Communication over the T1 systems occurs via transmission of T1 frames.
A typical T1 circuit which may require testing is a T1 coder-decoder (Codec), such as the National Semiconductor Company model TP 3064 Codec. A Codec is a T1 circuit which interfaces between the network and a telephone and serves to convert analog signals to digital (A/D) and digital signals to analog (D/A). In the digitizing process, the Codec samples the analog signal at the rate of 8 KHz. Thus, for instance, eight samples would be required to digitize a 1 KHz analog signal. These eight samples would be inserted in the same channel position of eight consecutive T1 frames. The general procedure for digitizing a given analog signal with a Codec is as follows: (1) generate the voltage sample of the sine wave for each sampling interval of time; (2) convert the voltage sample to the appropriate pulse code modulated (PCM) eight bit code, that is, digitize the sample; (3) insert the eight bit digitized sample value into the proper channel position of a 24-channel T1 frame; (4) repeat steps 1 through 3 for the next sample value. This procedure, however, becomes exceedingly tedious and time consuming, even for relatively "simple" signals like a sinusoidal frequency. For instance, sampling a 1010 Hz signal at a sampling rate of 8 KHz would require 800 samples before the samples would begin to repeat themselves. These 800 samples would be inserted in the same channel position of 800 consecutive T1 frames. This amounts to 800.times.193=154,400 bits of information which would be necessary to test a Codec to determine if it properly digitized a 1010 Hz signal. In addition, the PCM analog-to-digital conversion process may require application of a complex transfer function. (See the International Telegraph and Telephone Consultative Committee (CCITT) Red Book, Vol. III, Fascicle III.3, Tables 1a/G.711 & 1b/G.711 (A-law) and 2a/G.711 & 2b/G.711 (Mu-law).) Finally, this information must be converted (one bit at a time) to the corresponding test pattern language which the given circuit board tester requires.
It has been prior art practice to generate such data "manually", that is, a test programmer has had to calculate the necessary serial frame test data and transform it into test pattern language information which the given circuit board tester can accept. Thus, for a given serial device, the test programmer must generate the sample data, generate the serial frames from the sample data, and then generate the test data from the serial frames. Obviously, generating such large amounts of complex telecommunication serial frame test data is tedious and time consuming. (Generating such test data "manually" could very well consume weeks of an individual's time.) Moreover, ensuring the accuracy of the test data is very difficult and to the extent that there are doubts about the accuracy of the test data, the test results are suspect. The result has been that prior art testing of complex telecommunications circuits has been limited by the difficulty of generating sufficient amounts of accurate serial frame test data.